Store the contents of the accumulator register in the memory location specified in the operand address. and 32 wires corresponding to the grouped end. This handle slides over the four shoulder screws on top of the module and latches into place. The decision to cool the LVDC by circulating coolant through the walls of the computer was unique at the time and allowed the LVDC and LVDA (part-cooled using this technique) to be placed in one cold plate location due to the three dimensional packaging. Photo courtesy of. This stack is at the US Space & Rocket Center. Writing to core memory required additional wires called the inhibit lines. The wiring is visible inside the broken module as well as one of the tiny silicon dies (on the right). Closeup of the Y driver board showing six ULD modules and six transistor pairs. The clock driver boards are below the core memory stack but above the inhibit board. Another fascinating article, bravo! on a trajectory towards the Moon. The inhibit board is on the underside of the core module and holds Semiconductor chips of 0.025 by 0.025 inches (0.64 mm × 0.64 mm), each containing either one transistor or two diodes, were reflow soldered to the top side. One interesting feature of the simplex and duplex memory modes is that the software could switch between them while running, even setting John S: I believe the LVDC was heavily influenced by IBM's S/360 technology. We don’t mean a super-modern scientific calculator, either. They are matrixed with 8 drivers at one end and 8 at the other end. This module stored 4K words of 26 data bits and 2 parity bits. For some values of scale, though the timing can get hairy.Anyway, thanks for doing this, so darn instructive!John. [2][10][11] Copper balls were used for contacts between the chips and the conductive patterns.[6]:509. The diode board is connected to 64 Y select lines, but each line has two ends. 8 bits of the address specified a word within a sector, and the 9th bit selected between the software-selectable "current sector" or a global sector called "residual memory". advent of semiconductor DRAMs. It features 63,488 GB of RAM and has Ubuntu 14.4 operating system. The address is within the current instruction sector; the 9th (residual) bit of the operand selects the syllable. The contents of core memory are retained when the power is disconnected, so it's likely that the module still holds the software from The inhibit driver is similar to the current sink in the EI driver, so I suspect the ID-2 module is being used to boost the current. The TCV control voltage is fed into each EI module, causing the current to (Keep in mind that reading from core memory erases the data, so a memory access consists of a read followed by a write to restore the data.) two on the left and two on the right. If the resulting voltage is above a threshold, the output is triggered. The four flat cables between the X diode matrix and the core planes went vertically, from the top and bottom of the matrix. compared to 23.4 µs for the AGC. There are 8 high drive signals and 8 low drive signals generating the 64 Y select lines through the core stack. I was just now watching a video on the same thing on Smarter Everyday 2 channel where Luke Talley was explaining these things. MIT argued that the LVDC wasn't powerful enough to replace the AGC. ↩, One question is why did IBM use SLT modules instead of integrated circuits? inner diameter was 19 mils and their outer diameter was 32 mils (0.8 mm). The flex cables between the diode matrices and the core stack are not visible: The AGC's core memory was only 2K words. I also have an RSS feed. Each plane had one inhibit line threaded through all the cores in the plane. The photo below shows the sense amplifier board on top of the module.17 along with the Abort Guidance System, an emergency backup computer. The Command Module contained one AGC while the Lunar Module contained a second AGC7 The core stack itself was very similar between the LVDC and the S/360 machines; the difference in weight and volume comes from the Multiply the contents of the memory location specified in the operand address by the contents of the accumulator register. By selecting a different pair of drivers, a different line is energized. Note that this die is much less complex than even a basic integrated circuit. The data bits exit the sense amplifier boards through the flex cable on the right. Proceedings of the Fall Joint Computer Conference, 1964, pages 501-516. Up to 35 alumina squares of 0.3 by 0.3 by 0.07 inches (7.6 mm × 7.6 mm × 1.8 mm)[8] could be reflow soldered to a board. M.M. "Mechanical and Electronic Packaging for a Launch-Vehicle Guidance Computer." The complete module was called a unit logic device. The schematic shows several MCD (Memory Clock Driver) modules, but I can't see any modules on the boards. They did that anyway with their automotive electronics, so it's not surprising you can't find any info on those components. The 14-wire flex cable on the right connects the drivers to the 14 inhibit wires in the core stack. These are wired up in a "matrix" configuration so each combination of a high driver and a low driver selects a different line. The cold plates used to cool most equipment in the Instrument Unit were inefficient from a space view although versatile for the variety of equipment used. Core memory was built from tiny ferrite rings called cores, storing one bit in each core by The photo below shows the internal components of a ULD module. NASA's incredible Saturn V rocket propelled dozens of humans toward Earth's moon. This mission required the three-stage Saturn V rocket, the most powerful rocket ever built. The sense amplifier board on top of the memory module. The first one describes the memory module: and Saturn V Computer ring: in the rocket itself. In a large array, this approach significantly reduces the number of line drivers required. The LVDC could also respond to a number of interrupts triggered by external events. Photo from, An exploded view of the memory module showing the key components. The high-precision 20.8Ω resistors at the top and Business computers often used 6-bit characters, while aerospace computers typically used whatever word size provided the necessary The LVDC was approximately 30 inches (760 mm) wide, 12.5 inches (320 mm) high, and 10.5 inches (270 mm) deep and weighed 80 pounds (36 kg). Memory was broken into 256-word "sectors". There is an important difference between the X and Y wiring. visibility, a change in the circuitry, or another board with these modules. For writing, a single inhibit wire (explained below) runs through all the cores parallel to the X wires. Doing the math, the LVDC has 1/12 the weight and 1/40 the volume per byte. This memory module was technologically advanced for the mid-1960s, using surface-mount components, hybrid modules, and flexible connectors that The AGC's circuit boards were encapsulated into rectangular modules, while the LVDC's circuit boards plugged into a backplane in The Saturn V rocket was 111 meters (363 feet) tall, about the height of a 36-story-tall building, and 18 meters (60 feet) taller than the Statue of Liberty. , a mouse or keyboard), output for the user ( e.g. While the hardware would be fairly simple to emulate, the only remaining copies of the software are probably in the core memory of the Instrument Unit LVDCs of the remaining Saturn V rockets on display at NASA sites. Unlike a modern 'jump' instruction the operand address did not actually specify the address to jump to, but pointed to a 26-bit 'HOP constant' which specified the address. ↩, The LVDC has 26-bit words, each word consisting of two 13-bit syllables. Saturn V was an American super heavy-lift launch vehicle certified for human-rating used by NASA between 1967 and 1973. At its center, the core memory module contains the stack of 14 core planes shown earlier. a more standard way. There are 8 electrical connectors and two connectors for liquid cooling. The LVDC and associated hardware used more than 50 different types of ULDs. Each plane had a separate sense line for reading, and a separate inhibit line for writing. Using a separate wire to flip each core would be impractical, but in the 1950s a technique called The sense wires cross over in the middle of the plane; this reduces induced noise because noise from one half of the plane cancels out noise from the other half. These modules were a variant of the SLT (Solid Logic Technology) modules developed for IBM's popular S/360 series of computers. International Electronic Circuit Packaging Symposium 21–24 August 1964. We’re literally talking about the processing power of a calculator from 1998, which boasted eight times the RAM of Apollo’s guidance computer. The top edge of the board has a 24-wire flex cable to the diode matrix, with a second 24-wire cable at the bottom. Core Memory Module, Saturn V This is a core memory module, unflown, from a Launch Vehicle Digital Computer, part of the guidance system for the Saturn V rocket. While SLT modules had resistors on the upper surface, ULD modules had resistors underneath, increasing the density but also the cost. ↩. In 1963, SLT modules had cost and performance advantages over integrated circuits. It could keep track of eight registers, the Apollo Guidance Computer … In particular, the computer's logic contains In the write process, a current passed through the X and Y lines, flipping the selected cores (one per plane) to the 1 state, storing all 1's in the word. The minimum requirements for the hardware specifications are a 650MHz processor, 64MB of RAM, a 4GB hard drive, a CD ROM drive, 56KB fax modem and a 17″ monitor. Thus, the 8 high drivers and 8 low drivers select one of the 64 (8×8) Y lines. While this photo shows three wires through each core, the LVDC used four wires. The sense line was used to read the contents of the bit, while the inhibit line was used to write a 0 (by inhibiting the writing of a 1).9, In this section, I'll explain how the LVDC core memory module was physically constructed. Core memory as a whole died out in the 1970s with the IBM engaged in political battles, attempting to replace MIT's AGC with the LVDC. Logically AND the contents of the accumulator with the contents of the memory location specified in the operand address. Chinese ROMhacker YZB has coded a high-level hack of the Sega Saturn Castlevania: Symphony of the Night [Akumajou Dracula X-Gekka no Yasoukyoku] which implements a number of quality of life improvements by using the 4MB RAM cart and other modifications: Disk-reading slowdown is improved by preloading data to a 4MB RAM cart, the CD file layout is optimized, and several other … This page was last edited on 14 April 2021, at 01:45. To summarize, a core memory plane had four wires through each core: X and Y drive lines, a sense line, and an inhibit line. SMS cards were IBM's previous generation of circuit cards and normally used discrete germanium transistors. Save money on one of 2 used Saturn Outlooks in Anaheim, CA. One big architectural difference was that the LVDC was a serial computer, operating on one bit at a time, while the circuit board held the ULD module in place and connected with these contacts.5 A select line is driven by activating an EI module in voltage mode at one end of the line and an EI module in current mode at the other end. This computer controls all the timing; start engine, stop engine, fire separation, fire retro rockets, all this kind of stuff. The "showdown" is described in more detail here. Core memory was the dominant form of computer storage from the 1950s until it was replaced by semiconductor memory chips in the 1970s. [4], Unlike the Apollo Guidance Computer software, the software which ran on the LVDC seems to have vanished. The flight computer had only 32k of memory - today's home computers have 100 times as much. Pages 226-241. Fully fueled for liftoff, the Saturn V weighed 2.8 million kilograms (6.2 million pounds), the weight of about 400 elephants. they had the desired resistance. Serial is easier to make fast, but parallel is easier to scale. Core memory was built from tiny ferrite rings called cores, In "duplex" mode, each word was stored in two memory modules. The AGC's backplane was wire-wrapped by machine, while the LVDC's backplane was a 14-layer printed circuit board. However, memory only needed to be doubly Thus, the drive signals are in pairs, one from the "E" side (voltage source) of the EI chip and one from the "I" side (current sink). the EI modules. A sensor in the stack detects the temperature, causing a TCV regulator (Temperature Controlled Voltage) to generate a voltage Was the LVDC building upon IBM's experience with laying out multilayer boards with the S/360 (and earlier systems) when they built this? Advertisements may come up at the start of the videos, since they do not allow embedding. Thus, there are 256 diodes in the matrix, as well as 32 diodes associated with the 16 groups. In contrast, the ULD modules examined by Fran Blanche ↩, The SLT modules in my photograph are mounted on an SMS card, rather than the expected SLT card. By 1969, IBM started using integrated circuits, which they called MST (Monolithic Systems Technology). Thanks a lot Ken. This allowed a grid of X and Y lines to select one core from the grid. "cordwood" and allows the components to be packed together closely. Y lines that pass through the core stack. ↩, Much of the memory-related circuitry is in the LVDC's computer logic, not the memory module itself. The Saturn V rocket was 111 meters (363 feet) tall, about the height of a 36-story-tall building, and 18 meters (60 feet) taller than the Statue of Liberty. By energizing an X line and a Y line, one core in each plane was selected. sense lines, detect errors, and generate necessary clock signals.11. However, SLT modules were viewed outside IBM as backward compared to integrated circuits. Apollo Study Report, Volume 2, pages 3-36 to 3-37. To see the need for diodes, note that in the example above [citation needed]. The cable on the right links the driver board to the rest of the computer via the I/O board. All of the 14-pin 54-series parts had VCC on pin 4 and GND on pin 11, vs. 14 and 7 respectively for the 74-series brethren. Contents of accumulator are shifted by up to two bits, based on a value in the operand address. The LVDC mounted in a support frame. The inhibit board on the bottom of the memory module. One of the transistors has been dislodged, a ULD module has been broken in half, and the other ULD module is cracked. [5] The chassis was made of magnesium-lithium alloy LA 141, chosen for its high stiffness, low weight, and good vibration damping characteristics. The clock driver is a pair of boards that generate the timing signals for the memory module. A core memory module from the LVDC. Odd parity had the advantage that parity would catch a word that was stuck all 0's or all 1's. I hate to be pushy but I was not sure that you would see or possibly reply to a question I just asked on your post about the one-wire protocol and the Magsafe connector. Thus, the value of the bit in the core was read by resetting the core to 0 and testing the sense wire. separate modes for instructions and data. Note that the LVDC's circuitry was triply-redundant to detect and correct errors. The closeup below shows that the board has suffered some component damage. The AGC provided computation and electronic interfaces for guidance, navigation, and control of the spacecraft. The "EI" module is the heart of the driver; [1] Instructions were one syllable in size, while data words were two syllables (26 bits). guiding and controlling the Saturn V rocket. Because there are twice as many X lines, the module has a second X driver board underneath the one visible below. If driver B is energized positive and driver 1 is energized negative, current flows through the core line highlighted in red. However, even after the introduction of SLT in 1964, IBM needed to support older computers with SMS cards. Transfer execution to the operand address specified if the accumulator contents are negative. Closeup of X diode matrix showing diodes mounted vertically using cordwood construction between two printed circuit boards. The log book for the LVDC at National Air and Space Museum says the dimensions were 31x13.1x13 inches and the weight was 90 pounds. damaged circuitry poses a problem so the contents will probably remain locked inside the memory module for decades more. It would be interesting to compare production runs.The next big question is the serial LVDC processor architecture versus the parallel design of the AGC processor architecture. The LVDC core planes were similar but not identical to the S/360 Model 50 core planes. These dies, along with thick-film printed resistors, were mounted on a half-inch-square ceramic wafer to measuring 62.5"×26"×60". Weighing in at 70 lbs, it had 2 Kbits of memory and ran at roughly 2MHz (roughly 1/8th of an Arduino at a fraction of the size and weight). saturn ib and saturn v computer programs, software status report (nasa -tm-x-729c 1) saturn 1e anl satufn 5 ccpeutee fecgea cs , sc fiwape status eeport (nasa) 78 f hc $5. The round connectors are visible on the front side of the computer. The two lower circles were doped (darker regions) to form the anodes of the two diodes, while the upper-right circle was the cathode, connected to the substrate. To avoid doubling the number of diodes used, the X board only has a diode pair at one end of each of the 128 X lines. IBM started developing SLT modules in 1961, before integrated circuits were commercially viable, were filled with pink silicone inside. It does navigation and guidance. The two cables connected to the front side of the diode matrix wrap around to the far side of the stack, while the two cables connected Its master clock ran at 2.048 MHz, but operations were performed bit-serially, with 4 cycles required to process each bit, 14 bits per instruction phase, and 3 phases per instruction, for a basic instruction cycle time of 82 μs (168 clock cycles) for a simple add. but as you mention it's not as flexible. It was used in conjunction with the Launch Vehicle Data Adaptor (LVDA) which performed signal conditioning to the sensor inputs to the computer from the launch vehicle. However, the AGC also had 36K words of read-only storage in its hardwired core rope modules. Some examples are the Arma Micro D, dD17B and Magic 321. SLT modules (left) are considerably larger than ULD modules (right). Randa. SLT modules were also cheaper than comparable integrated circuits in the 1960s. the inhibit line prevents the core from flipping to a 1. S. Bonis, R. Jackson, and B. Pagnani. This meant that, for each of the seven stages, one module in any one of the three pipelines could fail, and the LVDC would still produce the correct results. These links provides some detail: Beyond Apollo: Moon Tech Takes a Giant Leap, Apollo Computer (1960). The Launch Vehicle Digital Computer (LVDC) is the one discussed in this blog post. Each line is driven by an ID-1 and ID-2 (Inhibit Driver) module and a pair of transistors. The LVDC had up to 8 core memory modules, holding 4K words each. A few instructions (such as multiply or divide) took several multiples of the basic instruction cycle to execute. The clock driver boards are on the bottom of the module, between the core stack and the inhibit board so it is hard to see the boards. Internally, the architecture of 8086 had 8 16-bit registers available to work with. This photo is a composite of top-lighting to show the die details, with back-lighting to show the sugar. Connections to the core plane are made through the pins around the outside. An MIB (Multilayer Interconnection Board) is a 12-layer printed circuit board. In the Smarter Every Day video How did NASA Steer the Saturn V?- Smarter Every Day 223 Destin is talking with Luke Talley about the memory modules used in the Saturn V LVDC computer. To write a 0 bit, the corresponding inhibit driver is activated and the current through Clips on the The titles were mostly limited to arcade ports from Capcom and SNK (Neo-Geo) and were only released commercially in Japan. Main memory was random access magnetic core, in the form of 4,096-word memory modules. Photo of a two-diode silicon die next to sugar crystals. "Saturn V Launch Vehicle Digital Computer and Data Adapter." The board also has error-detector (ED) modules that detect if more than one Y select line is driven at the same time. bottom of the board regulate the inhibit current. Although they superficially resembled integrated circuits, ULD modules contained multiple components. The two X driver boards are above the diode board, separated from it by foam. A core was magnetized by sending a pulse of current through wires threaded through the core. Contents of the accumulator are subtracted from the contents of the memory location specified in the operand address, and the result left in the accumulator. By energizing one X line and one Y line each with half the necessary current, only the core where both lines crossed would get enough current to flip leaving the other cores unaffected. By putting diodes on each line, reverse current paths such as 2 to A can be blocked. As far as a serial vs parallel processor, there were various other serial processors used for aerospace, presumably for weight reasons. 260 mA at 10 °C to 180 mA at 70 °C. The LVDC used odd parity. The S/360 used a mixture of PCB and wirewrap, which helped with field updates. Both computers used a 2.048 MHz clock, but the LVDC was considerably slower because it was serial: 82 µs for an add operation M.M. I can see that by the power and ground buses that connect to pins 4 and 11.It's likely they also had some Delco-specific part number stamped on each device. Although the X and Y boards have the same components, the wiring is different. Implementing this with digital logic would require a complicated set of gates to detect if two or more of the 8 inputs are high. This cartridge will allow you to play many of the best Saturn games that are otherwise unplayble without it. Note how the circuit boards are packed very closely together. Thus, alternating select lines go through the stack in opposite directions. The X diode matrix uses a different topology than the Y diode board to avoid doubling the number of components.16 For instance, the ULD modules were similar to SLT modules, but packaged differently. So awesome!! ↩, It's interesting to compare the AGC to the LVDC since they took two very different approaches to computer design and manufacture. At the bottom, the green 98-pin connector plugs into the LVDC's memory chassis, providing signals and power from the computer. … ... All of these printers are priced less than $500 at most major computer stores. , a monitor or speakers), and a control unit that coordinates the various The flat cables from the Y diode matrix went horizontally, from the sides of the matrix. ULD modules were considerably smaller than SLT modules, as shown in the photo below, making them more suitable for a compact space computer.4 Thus, executing a typical instruction requires three memory accesses: one for the instruction and two for the data. On the left, the circuit traces are visible on the ceramic wafer, connected to four tiny square silicon dies. This left it with sixteen possible opcode values when there were eighteen different instructions: consequently, three of the instructions used the same opcode value, and used two bits of the address value to determine which instruction was executed. One core plane for the LVDC's memory, holding 8192 bits. The LVDC was just one of several computers onboard the Apollo mission. Transfer execution to one of eight addresses dependent on the operand address, which also specifies modifications to the operand address of the next instruction before it is executed. These 32 signals go from the driver board to the diode matrix through two 16-wire flat cables. The currents canceled out, so the core in that plane would not flip to 1 but would remain 0. Find your perfect car with Edmunds expert reviews, car comparisons, and pricing tools. Closeup of an IBM 360 Model 50 core plane. Once the computer starts a memory operation, the various timing signals used by the memory module are generated asynchronously by the module's clock driver. There are 14 inhibit lines, one for each plane in the core stack. The die is very small; for comparison, grains of sugar are displayed next to the die. Those MSI chips are very likely space qualified mil-spec 54-series logic gates. Memory was in the form of 13-bit syllables, each with a 14th parity bit. It has 7 channels to read 7 bits from the memory stack; an identical board below processes another 7 bits, for 14 bits in total. Each channel consists of a differential amplifier and buffer, followed by a differential transformer and an Besides, space qualification is another layer of expense on top of mil certification. This technique is called In this way, the X and Y cables were attached to orthogonal sides of the core planes, connecting to the orthogonal X and Y wires. it sums the input voltages using a resistor network. On May 4 Saturn V personnel met in Washington to consider the Apollo reliability and quality assurance program. However, the current through the select line needs to go both ways, so cores can be flipped both directions. AGC operated on all bits in parallel (like most computers). An important characteristic of core memory was that the process of reading a core destroyed its value, so it needed to be re-written. But I do have some questions and comments. During the month MSFC completed a plan for integrating computer information from Saturn V systems, stages, and projects. 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